In recent years, a demand for liquid crystal display devices for use in large-screen liquid crystal TV sets as well as for use in portable telephones (such as mobile phones or cellular phones), notebook PCs, and monitors has expanded. As these liquid crystal display devices, the liquid crystal display devices with an active matrix driving system that enables high-resolution display are used. First, a typical configuration of the liquid crystal display device with the active matrix driving system will be outlined with reference to FIG. 6. In FIG. 6, a main configuration connected to one pixel in a liquid crystal display unit is schematically shown in the form of an equivalent circuit.
Generally, a display unit 960 of the liquid crystal display device with the active matrix driving system is constituted from a semiconductor substrate, an opposed substrate, and a structure with liquid crystals sealed therein between these opposed two substrates. In the semiconductor substrate, transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 (in the case of a color SXGA panel, for example, 1280×3 pixel rows×1024 pixel columns) are arranged in a matrix form. On the entire surface of the opposed substrate, one transparent electrode 967 is formed.
Turning on/off of a TFT 963 having a switching function is controlled by a scan signal. When the TFT 963 is turned on, a gray scale voltage corresponding to a video data signal is applied to a pixel electrode 964. The transmissivity of a liquid crystal changes due to a difference in potential between each of the pixel electrodes 964 and the opposing substrate electrode 967. Even after the TFT 963 has been turned off, the difference in potential is held at a liquid crystal capacitance 965 and an auxiliary capacitance 966 for a certain period, thereby displaying an image.
On the semiconductor substrate, data lines 962 that send a plurality of levels of voltage (gray scale voltages) applied to the respective pixel electrodes 964 and scan lines 961 that send scan signals are arranged in a matrix form (in the case of the color SXGA panel, 1280×3 data lines and 1024 scan lines are arranged). The scan lines 961 and the data lines 962 become large capacitive loads due to capacitances generated at mutual intersections and liquid crystal capacitances sandwiched with the opposing substrate electrode.
The scan signal is supplied to a scan line 961 by a gate driver 970, and supply of the gray scale voltage to each of the pixel electrodes 964 is performed from a data driver 980 through a data line 962. The gate driver 970 and the data driver 980 are controlled by a display controller 950. A clock CLK, a control signal, and the like are supplied to each of the gate driver 970 and the data driver 980 from the display controller 950. Video data is supplied to the data driver 980. Currently, digital data has become mainstream, as the video data. A supply voltage is supplied to each of the gate driver 970 and the data driver 980 from a supply voltage circuit 940.
Rewriting of data for one screen is performed in one frame period (usually, approximately 0.017 seconds), and each pixel row (each line) is selected one by one for each scan line. The gray scale voltage signal is supplied from each data line within the period of the selection.
While the gate driver 970 should supply at least a binary scan signal, the data driver 980 needs to drive the data line by the gray scale voltage signal of multi-valued levels corresponding to the number of gray scales. For this reason, the data driver 980 includes a decoder that converts the video data to an analog voltage and a digital-to-analog converter circuit (DAC) formed of an operational amplifier that amplifies the analog voltage and outputs the amplified analog voltage to a corresponding data line 962.
As a technique of driving a large-screen display device of the liquid crystal TV sets, a dot inversion driving scheme capable of realizing higher picture quality is adopted. In the dot inversion driving scheme, an opposing substrate electrode voltage VCOM is set to a constant voltage and voltage polarities held in adjacent pixels are mutually opposite in the display panel 960 in FIG. 6. For this reason, polarities of voltages output to the adjacent data lines 962 become positive-polarity and negative-polarity with respect to the opposing substrate electrode voltage VCOM. Since the data driver 980 in the dot inversion driving scheme must output positive-polarity and negative-polarity gray scale signal voltages, at least two voltage supplies having a potential difference which is approximately twice of the maximum value of a liquid crystal application voltage (that is a potential difference between a gray scale voltage and the opposing substrate electrode voltage) are supplied to the output amplifier of the data driver.
FIG. 7 is a diagram showing an example of a typical configuration of an output circuit for two outputs (formed of a positive-polarity output buffer amplifier, a negative-polarity output buffer amplifier, and an output switch circuit) in a data driver that performs dot inversion driving. In FIG. 7, two adjacent data lines (data line loads) 962-1 and 962-2 are respectively connected to driver output terminals P1 and P2. As shown in FIG. 7, this output circuit includes a positive-polarity output buffer amplifier (also simply abbreviated as a “positive-polarity amplifier”) 91, a negative-polarity output buffer amplifier (also simply referred to as a “negative-polarity amplifier”) 92, and an output switch circuit 300. A high-potential voltage supply VDD and a low-potential voltage supply VSS are supplied to the positive-polarity output buffer amplifier 91. Based on a positive-polarity reference voltage Vp, the positive-polarity output buffer amplifier 91 amplifies and outputs a positive gray scale voltage Vout1 to an amplifier output terminal N11. The high-potential voltage supply VDD and the low-potential voltage supply VSS are supplied to the negative-polarity output buffer amplifier 92. Based on a negative-polarity reference voltage Vn, the negative-polarity output buffer amplifier 92 amplifies and outputs a negative gray scale voltage Vout2 to an amplifier output terminal N12. The opposing substrate electrode voltage is set to be substantially intermediate between voltages of the high-potential voltage supply voltage VDD and the low-potential voltage supply voltage VSS.
The output switch circuit 300 includes switches SW11 and SW12, and switches SW21 and SW22. The switches SW11 and SW12 are respectively connected between the amplifier output terminal N11 and the driver output terminal P1 and between the amplifier output terminal N11 and the driver output terminal P2, and are respectively controlled by control signals S1 and S2. The switches SW21 and SW22 are respectively connected between the amplifier output terminal N12 and the driver output terminal P1 and between the amplifier output terminal N12 and the driver output terminal P2, and are respectively controlled on or off by the control signals S2 and S1. When the switches SW11 and SW22 to be controlled by the control signal S1 are turned on, the amplifier output terminals N11 and N12 are respectively connected to the driver output terminals P1 and P2. To the driver output terminals P1 and P2, the output voltage Vout1 of the positive-polarity output buffer amplifier 91 and the output voltage Vout2 of the negative-polarity output buffer amplifier 92 are respectively delivered.
When the switches SW12 and SW21 to be controlled by the control signal S2 are turned on, the amplifier output terminals N11 and N12 are respectively connected to the driver output terminals P2 and P1. Then, the output voltage Vout1 of the positive-polarity output buffer amplifier 91 and the output voltage Vout2 of the negative-polarity output buffer amplifier 92 are output to the driver output terminals P2 and P1, respectively.
In the configuration in FIG. 7, for respective polarities of signal voltages, the positive-polarity output buffer amplifier 91 and the negative-polarity output buffer amplifier 92 are provided. Connection to either the data line load 962-1 or the data line load 962-2 is switched by the output switch circuit 300, thereby performing polarity inversion driving. A differential input pair of each of the positive-polarity output buffer amplifier 91 and the negative-polarity output buffer amplifier 92 can be thereby composed by only N-channel transistors or P-channel transistors of a single conductivity type. An amplifier circuit configuration is thereby simplified, and an output deviation is thereby made uniform. In a Rail-to-Rail configuration with differential input pairs composed by both N-channel and P-channel transistor pairs, however, the output deviation deteriorates in the vicinity of power supply voltages.
In the dot inversion driving scheme in recent years, in order to reduce power dissipation due to a problem of heat generation in LSIs and a demand for energy saving, a driving scheme in which only N voltage polarities of a pixel sequence in a data line direction are set to be the same (for polarity inversion driving for each N horizontal periods) is being carried out. In this case, voltage polarities of adjacent data lines are mutually opposite. However, the N voltage polarities to be output to a same data line are the same.
In the polarity inversion driving scheme for each horizontal period (1H dot inversion), a positive-polarity gray scale voltage signal and a negative-polarity gray scale voltage signal are alternately output to a same data line. Thus, when the positive-polarity gray scale voltage signal is output, a charging operation is always performed. When the negative-polarity gray scale voltage signal is output, a discharging operation is always performed.
In the polarity inversion driving scheme for each N horizontal periods (NH dot inversion), N gray scale signals of a same polarity are output to a same data line. Even when the positive-polarity gray scale signals are output, the discharging operation is needed. Even when the negative-polarity gray scale voltage signals are output, the charging operation is needed. That is, each of the positive-polarity output amplifier 91 and the negative-polarity output amplifier 92 needs both of sufficient charging and discharging capabilities.
FIG. 8 is an output waveform diagram that explains an operation of the data driver in FIG. 7. In the 1H dot inversion, as shown in (a) of FIG. 8, the charging operation of the positive-polarity output buffer amplifier 91 and the discharging operation of the negative-polarity output buffer amplifier 92 are principally performed. For charge driving by the positive-polarity output buffer amplifier 91 and discharge driving by the negative-polarity output buffer amplifier 92, high driving capability is needed. A discharging operation of the positive-polarity output buffer amplifier 91 and a charging operation of the negative-polarity output buffer amplifier 92 only serve to prevent overshooting and undershooting, and hence high driving capability is not needed for the discharging operation of the positive-polarity output buffer amplifier 91 and the charging operation of the negative-polarity output buffer amplifier 92.
In 2 H dot inversion, as shown in (b) of FIG. 8, high driving capability of a certain degree is needed for the discharging operation of the positive-polarity output buffer amplifier 91 and the charging operation of the negative-polarity output buffer amplifier 92 as well as the charging operation of the positive-polarity output buffer amplifier 91 and the discharging operation of the negative-polarity output buffer amplifier 92.
FIG. 9 is a diagram showing an example of a typical configuration (related art) of the positive-polarity output buffer amplifier 91 in FIG. 7, and shows the configuration in which an output stage is formed of transistors of a same polarity. Referring to FIG. 9, a differential stage (input differential stage) includes a current source M90 which has a first terminal connected to a power supply terminal (VSS), N-channel transistors M91 and M92, a P-channel transistor M93 which has a source connected to a power supply terminal (VDD) and a drain connected to a drain of the N-channel transistor M91, and a diode-connected (gate and drain being coupled) P-channel transistor M94 which has a source connected to the power supply terminal (VDD), a gate connected to a gate of the P-channel transistor M93, and a connected to a drain of the N-channel transistor M92. Coupled sources of the N-channel transistors M91 and M92 are connected to a second terminal of the current source M90. Gates of the N-channel transistors M91 and M92 receive an input voltage Vin and a output voltage Vout which is fed backed, respectively.
An intermediate stage includes a P-channel transistor M95 which has a source connected to the power supply terminal (VDD) and a gate connected to an output node (drain of the transistor M91) of the differential stage, and a current source M96 connected between a drain of the P-channel transistor M95 and the power supply terminal (VSS).
An output stage includes a P-channel transistor M97 which has a source connected to the power supply (VDD) and a gate connected to the output node (drain of the transistor M91) of the differential stage and a P-channel transistor M98 which has a drain connected to the power supply terminal (VSS), a gate connected to the drain of the P-channel transistor M95, and a source connected to a drain of the P-channel transistor M97. A connection node of the drain of the P-channel transistor M97 and the source of the P-channel transistor M98 is an output terminal of the positive-polarity output buffer amplifier 91.
The configuration of the differential amplifier shown in FIG. 9 is simple and area saving. The P-channel transistor M98 in the output stage is of a source follower connection, and a short circuit current at a time of high-speed charging is small. However, there is a problem as a buffer amplifier that drives a large-screen liquid crystal display device. A description will be given about the problem below.
When a data line with a large capacitive load is driven with a high slew rate, the size (channel width) of each of the P-channel transistors M97 and M98 in the output stage is set to be sufficiently large. For this reason, when current of the current source 96 is small, a gate potential at the P-channel transistor M98 cannot be quickly changed due to a gate parasitic capacitance of the P-channel transistor M98. That is, the problem of a shortage of discharging capability of the positive-polarity output buffer amplifier arises. Then, in order to increase the discharging capability of the P-channel transistor M98, it is necessary to increase static current dissipation of the current source M96. Power dissipation will be thereby increased.
As described above, the discharging capability of the positive-polarity output amplifier 91 in FIG. 9 is defined by the current value of the current source M96. Thus, when low power dissipation is to be implemented, the discharging capability is usually reduced (which also holds true for charging capability of the negative-polarity output amplifier 92). On the other hand, in order to increase the discharging capability of the positive-polarity output amplifier 91, a current value of the current source 96 should be increased. However, a problem may arise that static power dissipation of each amplifier is increased (which also holds true for the charging capability of the negative-polarity output amplifier 92).
As a configuration of an amplifier in which static power dissipation of the amplifier is comparatively small and discharging capability of the positive-polarity output amplifier 91 is high, an AB-class output circuit disclosed in Patent Document 1 listed below is known. FIG. 10 is a diagram showing a configuration of the AB-class output circuit in Patent Document 1 listed below. Referring to FIG. 10, an output stage includes a P-channel transistor M87 connected between a high-potential power supply terminal (VDD) and an output terminal ND1 and an N-channel transistor M88 connected between the output terminal ND1 and a low-potential power supply terminal (VSS). The output stage drives the output terminal ND1 with high charging capability and with high discharging capability. A gate node NP1 of the P-channel transistor M87 is connected to an output of a driver 70 that receives an input signal Vin. The P-channel transistor M87 performs a charging operation. A change in the input signal Vin is transmitted to a gate node NN1 of the N-channel transistor M88 through an intermediate stage (formed of current sources M83 and M84). The N-channel transistor M88 performs a discharging operation. The intermediate stage includes a P-channel floating current source M83 and N-channel floating current source M84, and current sources M81 and M82. Bias voltages BP2 and BN2 are supplied to gates of the P-channel floating current source M83 and the N-channel floating current source M84, respectively. The P-channel floating current source M83 and the N-channel floating current source M84 are connected between the gate node NP1 of the transistor M87 and the gate node NN1 of the transistor M88. The current source M81 is connected between the high-potential power supply VDD and the gate node NP1 of the P-channel transistor M87. The current source M82 is connected between the low-potential power supply VSS and the gate node NN1 of the N-channel transistor M88. A sum of currents of the floating current sources 83 and M84 is set to be substantially equal to current of each of the current sources M81 and M82.
When the terminal NP1 is changed to a lower potential in response to the input voltage Vin, the P-channel transistor M87 performs the charging operation. In this case, the current of the N-channel floating current source M84 is not changed, but the current of the P-channel floating current source M83 is reduced. Thus, the node NN1 is changed to a low potential, so that the discharging operation of the N-channel transistor M88 is stopped. Accordingly, the AB-class output circuit in FIG. 10 can perform a charging operation at high speed.
On the other hand, when the node (terminal) NP1 is changed to a higher potential in response to the input voltage Vin, the charging operation of the P-channel transistor M87 is stopped. In this case, the current of the N-channel floating current source M84 is not changed, but the current of the P-channel floating current source M83 is abruptly changed. Thus, the terminal NN1 is quickly changed to a higher potential, so that the N-channel transistor M88 performs the discharging operation. Accordingly, the AB-class output circuit in FIG. 10 can perform a discharging operation at high speed. When a relationship among the sum of the currents of the floating current sources M83 and M84, the current of the current source M83, and the current of the current source M84 is maintained, a static current dissipation value of each of the current sources M83 and M84 can be sufficiently reduced. Based on Patent Document 2 listed below that cites Patent Document 1 therein, the driver 70 can be formed of an N-channel differential pair. In this case, the driver in FIG. 10 can be replaced by the positive-polarity output amplifier 91 in FIG. 7.
Alternatively, by connecting an output terminal of the driver 70 to the node (terminal) NN1 and further by forming the driver 70 of a P-channel differential pair, the driver in FIG. 10 can also be replaced by the negative-polarity output amplifier 92 in FIG. 7.                [Patent Document 1] JP Patent Kokoku Publication No. JP-B-6-91379 (FIG. 1)        [Patent Document 2] JP Patent Kokai Publication No. JP-P2005-124120A (FIG. 1)        